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CAT24C208
8-Kb Dual Port Serial EEPROM FEATURES
I Supports Standard and Fast I2C protocol* I 2.5V to 5.5V operation I 16-byte page write buffer I Schmitt triggers and noise protection filters
DESCRIPTION
The CAT24C208 is an 8-Kbit Dual Port Serial CMOS EEPROM internally organized as 4 segments of 256 bytes each. The CAT24C208 features a 16-byte page write buffer and can be accessed from either of two separate I2C compatible ports, DSP (SDA, SCL) and DDC (SDA, SCL). Arbitration between the two interface ports is automatic and allows the appearance of individual access to the memory from each interface.
on I2C bus input
I Low power CMOS technology I 1,000,000 program/erase cycles I 100 year data retention I Industrial temperature range I RoHS-compliant 8-lead SOIC package
For Ordering Information details, see page 12.
BLOCK DIAGRAM
DSP VCC ARBITRATION LOGIC DDC VCC
DSP SCL DSP SDA
DISPLAY CONTROL LOGIC
D E C O D E R S
1K X 8 MEMORY ARRAY
D E C O D E R S
DDC CONTROL LOGIC
DDC SCL DDC SDA
VSS
CONFIGURATION REGISTER
EDID SEL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 1044, Rev. F
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CAT24C208
PIN CONFIGURATION
SOIC (W)
DSP VCC DSP SCL DSP SDA VSS 1 2 3 4 8 7 6 5 DDC VCC EDID SEL DDC SCL DDC SDA
PIN DESCRIPTION
Pin Number 1 2 Pin Name DSP VCC DSP SCL Function Device power from display controller The CAT24C208 DSP serial clock bidirectional pin is used to clock all data transfers into or out of the device DSP SDA pin and is also used to block DSP Port access when DDC Port is active. DSP Serial Data/Address. The bidirectional DSP serial data/address pin is used to transfer data into and out of the device from a display controller. The DSP SDA pin is an open drain output and can be wireOR'ed with other open drain or open collector outputs. Device ground. DDC Serial Data/Address. The bidirectional DDC serial data/address pin is used to transfer data into and out of the device from a DDC host. The DDC SDA pin is an open drain output and can be wire-OR'ed with other open drain or open collector outputs. The CAT24C208 DDC serial clock bidirectional pin is used to clock all data transfers into or out of the device DDC SDA pin, and is used to block DDC Port for access when DSP Port is active. EDID select. The CAT24C208 EDID select input selects the active bank of memory to be accessed via the DDC SDA/SCL interface as set in the configuration register. Device power when powered from a DDC host.
3
DSP SDA
4 5
VSS DDC SDA
6
DDC SCL
7
EDID SEL
8
DDC VCC
Doc. No. 1044, Rev. F
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C208
ABSOLUTE MAXIMUM RATINGS(1)
Temperature Under Bias .................. -55C to +125C Storage Temperature ........................ -65C to +150C Voltage on Any Pin with Respect to Ground(2) ............ -2.0V to +VCC + 2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Reliability Characteristics Symbol NEND(4) TDR(4) VZAP
(4)
Package Power Dissipation Capability (TA = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(3) ........................ 100mA
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Reference Test Method
Min
Typ
Max
Units Cycles/Byte Years Volts mA
MIL-STD-883, Test Method 1033 1,000,000 MIL-STD-883, Test Method 1008 JEDEC Standard JESD 22 JEDEC Standard 17 100 2000 100
ILTH(4)(5)
D.C. OPERATING CHARACTERISTICS
VCC = 2.5V to 5.5V, unless otherwise specified.
Symbol Parameter ICC ISB ILI ILO VIL VIH VHYS VOL1 VCCL1 VCCL2 Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Hysteresis Output Low Voltage (VCC = 3V) Leakage DSP VCC to DDC VCC Leakage DDC VCC to DSP VCC
Test Conditions fSCL = 100 KHz VIN = GND or either DSP or DDC VCC VIN = GND to either DSP or DDC VCC VOUT = GND to either DSP or DDC VCC
Min
Ty p
Max 3 50 10 10
Units mA A A A V V V
-1 VCC x 0.7 0.05 IOL = 3 mA
VCC x 0.3 VCC + 0.5
0.4 +100 +100
V A A
Note: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1044, Rev. F
CAT24C208
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Parameter Input/Output Capacitance (Either DSP or DDC SDA) Input Capacitance (EDID, Either DSP or DDC SCL) Conditions VI/O = 0V VIN = 0V Min Typ Max 8 6 Units pF pF
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
VCC = 2.5V to 5.5V, unless otherwise specified.
Read & Write Cycle Limits
Symbol FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF
(1)
Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
Min
Max 400 100 0.9
Units kHz ns s s s s s s ns ns
1.3 0.6 1.3 0.6 0.6 0 100 300 300 0.6 100
ns ns s ns
tSU:STO tDH
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Power-Up Timing(1)(2) Symbol tPUR tPUW Write Cycle Limits Symbol tWR Parameter Write Cycle Time Min Typ Max 5 Units ms Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Doc. No. 1044, Rev. F
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C208
FUNCTIONAL DESCRIPTION
The CAT24C208 has a total memory space of 1K bytes which is accessible from either of two I2C interface ports, (DSP_SDA and DSP_SCL) or (DDC_SDA and DDC_SCL), and with the use of segment pointer at address 60h. On power up and after any instruction, the segment pointer will be in segment 00h for DSP and in segment 00h of the bank selected by the configuration register for DDC. The entire memory appears as contiguous memory space from the perspective of the display interface (DSP_SDA and DSP_SCL), see Table 2, and Figures 11 to Figure 18 for a complete description of the DSP Interface. A configuration register at addresses 62/63h is used to configure the operation and memory map of the device as seen from the DDC interface, (DDC_SDA and DDC_SCL). Read and write operations can be performed on any location within the memory space from the display DSP interface regardless of the state of the EDID SEL pin or the activity on the DDC interface. From the DDC
interface, the memory space appears as two 512 byte banks of memory, with 2 segments each 00h and 01h in the upper and lower bank, see Table 1. Each bank of memory can be used to store an E-EDID data structure. However, only one bank can be read through the DDC port at a time. The active bank of memory (that is, the bank that appears at address A0h on the DDC port) is controlled through the configuration register at 62/63h and the EDID_SEL pin. No write operations are possible from the DDC interface unless the DDC Write Enable bit is set (WE = 1) in the device configuration register at device address 62h. The device automatically arbitrates between the two interfaces to allow the appearance of individual access to the memory from each interface. In a typical E-EDID application the EDID_SEL pin is usually connected to the "Analog Cable Detect" pin of a VESA M1 compliant, dual-mode (analog and digital) display. In this manner, the E-EDID appearing at address A0h on the DDC port will be either the analog or digital E-EDID, depending on the state of the "Analog Cable Detect" pin (pin C3 of the M1-DA connector). See Figure 1.
+5V DC (SUPPLIED BY DISPLAY) 10K 8 7 6 5 E-EDID EEPROM 1 2 3 4 I2C TO PROJECTOR/MONITOR DISPLAY CONTROLLER
M1-DA CONNECTOR
Figure 1.
28
DDC +5V
47.5K C3 27 26 DDC CLK DDC DATA
TO HOST CONTROLLER
FUSE, RESISTOR OR OTHER CURRENT LIMITING DEVICE REQUIRED IN ALL M1 DISPLAYS 8 HPD 2A MAX RELAY CONTACTS SHOWN IN DE-ENERGIZED POSITION
Table 1: DDC Interface
Table 2: DSP Interface
MEMORY ARRAY 01 Upper Bank 00 01 Lower Bank 00 Segment 1 256 Bytes Segment 0 256 Bytes Segment 1 256 Bytes 00 11 10 01 00
MEMORY ARRAY Segment 3 256 Bytes Segment 2 256 Bytes Segment 1 256 Bytes Segment 0 256 Bytes 00
00 Segment 0 256 Bytes Segment Pointer Address by No Segment Pointer Configuration Register (see Figure 19)
5
Segment Pointer No Segment Pointer
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Doc No. 1044, Rev. F
CAT24C208
I2C Bus Protocol The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of either SDA when the respective SCL is HIGH. The CAT24C208 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the respective SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24C208 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT24C208 is in a READ mode it transmits 8 bits of data, releases the respective SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24C208 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. After an unsuccessful data transfer an acknowledge will not be issued (NACK) by the slave (CAT24C208), and the master should abort the sequence. If continued the device will read from or write to the wrong address in the two instruction format with the segment pointers.
Figure 2. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9 BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACK SETUP ACK DELAY
Doc. No. 1044, Rev. F
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C208
DEVICE ADDRESSING
DDC Interface Both the DDC and DSP interfaces to the device are based on the I2C bus serial interface. All memory space operations are done at the A0/A1 DDC address pair. As such, all write operations to the memory space are done at DDC address A0h and all read operations of the memory space are done at DDC address A1h. Figure 3 shows the bit sequence of a random read from anywhere within the memory space. The word offset determines which of the 256 bytes within segment 00h is being read. Here the segment 00h can be at the lower or upper bank depending on the configuration register. Sequential reads can be done in much the same manner by reading successive bytes after each acknowledge without generating a stop condition. See Figure 4. The device automatically increments the word offset value (8-bit value) and with wraparound in the same segment 00h to read maximum of 256 bytes.
Figure 3. Random Access Read (Segment 00h only) WORD OFFSET
START 1010 0000 ACK A7 - A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP
Figure 4. Sequential Read (Segment 00h only)
WORD OFFSET
START 1010 0000 ACK A7 - A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ......... DATAN NOACK STOP
Figures 5 and 6 show the byte and page write respectively. The configuration register must have the WE bit set to 1 prior to any write on DDC Port. Only the segment 00h can be accessed of either lower or upper bank. Figure 5. Byte Write (Segment 00h only) WORD OFFSET
START 1010 0000 ACK A7 - A0 ADDRESS ACK DATA ACK STOP
Figure 6. Page Write (Segment 00h only) WORD OFFSET
START 1010 0000 ACK A7 - A0 ADDRESS ACK DATA0 ACK ......... DATA15 ACK STOP
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1044, Rev. F
CAT24C208
The segment pointer is at the address 60h and is writeonly. This means that a memory access at 61h will give undefined results. The segment pointer is a volatile register. The device configuration register at 62/63 (hex) is a non-volatile register. The configuration register will be shipped in the erased (set to FFh) state. The segment pointer is used to expand the available DDC address space while maintaining backward compatibility with older DDC interfaces such as DDC2B. For each value of the 8-bit segment pointer one segment (256 bytes) is available at the A0/A1 pair. The standard DDC 8-bit address is sufficient to address each of the 256 bytes within a segment. Note that if the segment pointer is set to 00h then the device will behave like a standard DDC2B EEPROM. Read and write with segment pointer can expand the addressable memory to 512 bytes in each bank with wraparound to the next segment in the same bank only. The two banks can be individually selected by the configuration register and EDID Sel pin, as shown in figure 19. The segments are selected by the two bits S1S0 = 00 or 01 in the segment address. Figures 7 to 10 show the random read, sequential read, byte write and page write.
Figure 7. Random Access Read
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK ACK START 1010 0001 ACK DATA NOACK STOP
Figure 8. Sequential Read
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK ACK START 1010 0001 ACK DATA0 ACK ...... DATAN NOACK STOP
Figure 9. Byte Write
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK ACK DATA ACK STOP
Figure 10. Page Write
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK ACK DATA0 ACK .......... DATA15 ACK STOP
Doc. No. 1044, Rev. F
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C208
DSP Interface The DSP interface is similar to I2C bus serial interface. Without the segment pointer, the maximum accessible memory space is 256 bytes of segment 00h only. In the Figure 11. Random Access Read
START 1010 0000 ACK A7 - A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP
sequential mode the wrap around will be in the same segment also. Figures 11 to 14 show the read and write on the DSP Port.
Figure 12. Sequential Read
START 1010 0000 ACK A7 - A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ..... DATAN NOACK STOP
Figure 13. Byte Write
START 1010 0000 ACK A7 - A0 ADDRESS ACK DATA ACK STOP
Figure 14. Page Write
START 1010 0000 ACK A7 - A0 ADDRESS ACK DATA0 ACK ...... DATA15 ACK STOP
The segment pointer is used to expand the available DSP port addressable memory to 1k bytes, divided into four segments of 256 bytes each. The four segments are
selected by two bits S1S0 = 00, 01, 10, 11 in the segment address. Figures 15 to 18 show the random read, sequential read, byte write and page write.
Figure 15. Random Access Read
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK ACK START 1010 0001 ACK DATA NOACK STOP
Figure 16. Sequential Read
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK START ACK 1010 0001 ACK DATA0 ACK ....... DATAN NOACK STOP
Figure 17. Byte Write
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK ACK DATA ACK STOP
Figure 18. Page Write
START START 0110 0000 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 - A0 ADDRESS ACK DATA0 ACK ACK ...... DATA15 ACK STOP
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1044, Rev. F
CAT24C208
ARBITRATION
The device performs a simplistic arbitration between the DDC and DSP ports. While the arbitration scheme described is not foolproof, it does prevent most errors. Arbitration logic within the device monitors activity on DDC_SCL and DSP_SCL. When both I2C ports are idle, DDC_SCL and DSP_SCL are both high and the arbitration logic is inactive. When a START condition is detected on either port, the opposite port SCL line is pulled low, holding off activity on that port. When the initiating SCL line has remained high for one full second, the arbitration logic assumes that the initiating devices is finished and releases the other SCL line. If the noninitiating device has been waiting for access, it can now read or write the device.
CONFIGURATION REGISTER
MSB Register Function Configuration Register 7 X 6 X 5 X 4 X 3 WE 2 AB1 1 AB0 LSB 0 NB
Function Description: NB: Number of memory banks in DDC port memory map. 0 = 2 Banks, 1 = 1 Bank AB0: Active Bank Control Bit 0 (See Figure 19) AB1: Active Bank Control Bit 1 (See Figure 19) WE DDC: Write Enable 0 = Write Disabled, 1= Write Enabled
Note: WE affects only write operations from the DDC port, not the display port. The display port always has write access.
Figure 19. Configuration Register Truth Table
AB1 0 0 1 1 X AB0 X X 0 1 X NB 0 0 0 0 1 EDID Select Pin 0 1 X X X Active Bank Lower Bank Upper Bank Lower Bank Upper Bank Lower (only) Bank
The configuration register is a non-volatile register and is available from either DSP or DDC port at address 62h/ 63h for write and read resp. Figure 20. Read Configuration Register
START 0110 0011 ACK DATA NO ACK STOP
Figure 21. Write Configuration Register
START 0110 0010 ACK DUMMY ADDRESS ACK XXXX WE AB1 AB0 NB ACK STOP
Doc. No. 1044, Rev. F
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C208
PACKAGING INFORMATION 8-Lead 150 MIL SOIC (W)
E1 E
D
h x 45 C A 1
e b
A1 L
SYMBOL A1 A b C D E E1 e h L 1
MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80
NOM
MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 BSC 0.25 0.40 0 0.50 1.27 8
8-LEAD_SOIC.eps
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1044, Rev. F
CAT24C208
EXAMPLE OF ORDERING INFORMATION
Prefix CAT Device # 24C208 Suffix W I - G T3
Company ID
Product Number 24C208 Package W: SOIC
Temperature Range I = Industrial (-40C to 85C)
Tape & Reel T: Tape & Reel 3: 3000/Reel
Lead Finish G: NiPdAu (PPF)
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) This device used in the above example is a CAT24C208WI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel) (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. 1044, Rev. F
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
REVISION HISTORY
Date 2/18/2004 Rev. C Reason Changed volt operation to 3V to 5.5V Updated Block Diagram Updated Pin Descriptions Updated DC Operating Characteristics Updated AC Characteristics Changed/Added figures 3 - 21 Updated Ordering Information Updated Function Description Updated Ordering Information Update Title Update Features Update Description Updated DC Operating Characteristics Updated AC Characteristics Update Arbitration Updated Example of Ordering Information Update Features Update Pin Configurations Update Absolute Maximum Ratings Update Reliability Characteristics Update DC Operating Characteristics Update Figure 2 Update Package Drawing Update Example of Ordering Information
03/25/2005 06/22/06
D E
06/28/06
F
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Publication #: Revison: Issue date:
1044 F 06/28/06

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